1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device having an SOI (silicon on insulator) structure which is formed by laterally growing single crystals from seed crystals on an insulating film, and a method of fabricating the same.
2. Description of the Background Art
Generally known is a semiconductor pressure sensor or a semiconductor acceleration sensor having an SOI structure, which is obtained by laterally growing single crystals from seed crystals on an insulating film for forming a single crystal layer and preparing a pressure-sensitive resistances (piezo resistances) having piezo characteristics from the single crystal layer. A conventional semiconductor pressure or acceleration sensor having such an SOI structure can operate under a high temperature since no p-n junctions are employed for electrically isolating the piezo resistances from each other and from a single crystal silicon substrate. The method of forming a single crystal layer of the SOI structure by laterally growing single crystals from seed crystals on an insulating film is called lateral seeding. As a method of such lateral seeding, known is laser recrystallization of irradiating a non-single crystal silicon layer which is formed on an insulating film with a laser beam for melting and resolidifying the same. Such laser recrystallization is widely employed since it is possible to form a high quality SOI structure at a low cost and a laser recrystallization apparatus is easy to handle. In order to form a single crystal semiconductor layer by laser recrystallization, it is necessary to cause recrystallization from seed crystal regions by controlling temperature distribution in the melted semiconductor material. Namely, crystallization progresses from low temperature regions toward high temperature parts in the melted silicon, and hence it is necessary to control temperature distribution so that the seed crystal regions are at low temperatures. A method using antireflection films is known as a method of controlling such temperature distribution, as described in detail in U.S. Pat. No. 4,822,752, for example.
FIG. 12 is a fragmented perspective view for illustrating a conventional laser recrystallization method using antireflection films. FIGS. 13 and 14 are sectional views for illustrating first and second steps of the conventional laser recrystallization method using antireflection films. FIG. 15 is a fragmented perspective view for illustrating a third step of the conventional laser recrystallization method using antireflection films. With reference to FIGS. 12 to 15, the conventional laser crystallization method using antireflection films is now described.
First, an insulating layer 102 of a silicon oxide film is formed on a surface of a single crystal silicon substrate 101, as shown in FIG. 12. This insulating layer 102 is provided in its prescribed regions with openings 15, which define seed portions. A non-single crystal semiconductor layer (polycrystalline silicon layer) 113 is formed on a surface of the insulating layer 102, and partially in the openings 105. Antireflection films 105 of prescribed shapes are formed on a surface of the polycrystalline silicon layer 113. These antireflection films 104 are formed by silicon nitride films (Si.sub.3 N.sub.4), for example. The antireflection films 104 are formed on positions separated from the openings 15, which are provided in the insulating layer 102, at substantially equal spaces. In order to suppress deformation of the surfaces during recrystallization, a thin cap film may be formed over the entire surfaces of the polycrystalline silicon layer 113 and the antireflection films 104. The openings 105 are filled up with parts of the polycrystalline silicon layer 113, which is made of a non-single crystal semiconductor material. Therefore, the crystal orientation of the polycrystalline silicon layer 113 to be recrystallized is controlled along that of the single crystal silicon substrate 101. Reflection factors of the silicon nitride films forming the antireflection films 104 periodically exhibit maximum values and zero depending on thicknesses thereof. In consideration of such properties, silicon nitride films having thicknesses zeroing reflection factors are employed as the antireflection films 104. According to this example, the antireflection films 104 are prepared from silicon nitride films having thicknesses of about 600 .ANG..
Then, the overall surface of the polycrystalline silicon layer 113 is irradiated with a laser beam 170, as shown in FIG. 13. The antireflection films 104 selectively formed on the surface of the polycrystalline silicon layer 113 have reflection factors of zero with respect to the laser beam 170. This means that the antireflection films 104 absorb substantially all incident light. On the other hand, regions provided with no antireflection films 104, i.e., those partially exposing the surface of the polycrystalline silicon layer 113, have reflection factors of about 40% with respect to the laser beam 170. Thus, the laser beam 170 which is applied to the overall surface of the polycrystalline silicon layer 113 is greatly absorbed in portions located under the antireflection films 104, to heat such regions to higher temperatures. The laser beam 170 has a wavelength of 488 nm and a beam diameter of about 120 to 180 .mu.m. The insulating film 102 is formed by a silicon oxide film having a thickness of 1 to 3 .mu.m, while the polycrystalline silicon layer 113, serving as a non-single crystal semiconductor layer, has a thickness of about 0.6 .mu.m. The antireflection films 104, which are about 5 .mu.m in width, are at positional spaces of about 15 .mu.m. The laser beam 170 which is applied onto the surface of the polycrystalline silicon layer 113 moves at a constant speed. The polycrystalline silicon layer 113 irradiated with the laser beam 170 is increased in temperature and melted. FIG. 16 is a temperature distribution diagram showing relations between surface positions and internal temperatures of the polycrystalline silicon layer 113. Referring to FIG. 16, it is understood that the polycrystalline silicon layer 113 has higher internal temperatures in the portions located under the antireflection films 104. In other words, the polycrystalline silicon layer 113 has lower internal temperatures in portions close to the openings 105.
After passage of the laser beam 170, the melted polycrystalline silicon layer 113 is cooled, as shown in FIG. 14. Thus, the temperatures of the melted polycrystalline silicon layer 113 start lowering, to be recrystallized (solidified) from regions having lower temperatures. As understood from the temperature distribution shown in FIG. 16, the polycrystalline silicon layer 113 has lower inner temperatures in the portions close to the openings 105. In this cooling process, therefore, the portions of the polycrystalline silicon layer 113 which are filled up in the openings 105 define seed portions 106. Thus, recrystallization of the polycrystalline silicon layer 113 is started from the seed portions 106. The seed portions 106 are connected with the single crystal silicon substrate 101. Therefore, single crystal silicon regions 103a having the same crystal orientation as the single crystal silicon substrate 101 spread from the seed portions 106, serving as start points, around the same.
Then, the completely recrystallized polycrystalline silicon layer 113 is converted to a homogeneous single crystal silicon layer 103, as shown in FIG. 15. Thereafter the antireflection films 104 are removed.
In the aforementioned formation of the single crystal silicon layer 103, recrystallization of the polycrystalline silicon layer 113 starts from the seed portions 106 located between the antireflection films 104 to progress toward the portions, which are at higher temperatures, located under the antireflection films 104. Therefore, crystals grown from both sides of the antireflection films 104 collide with each other in the portions located under the antireflection films 104. Consequently, crystal sub-grain boundaries 150 are defined in positions of such collision of the as-grown crystals. Namely, portions of the single crystal silicon layer 103 which are adjacent to each other through the antireflection films 104 are grown independently of each other, and hence such portions slightly deviate in crystal orientation from each other. As the result, the crystal sub-grain boundaries 150 are defined between such portions.
In the aforementioned laser recrystallization using the antireflection films 104, a single crystal silicon substrate having a major surface of a (100) plane is generally employed so that the stripes of the antireflection films 104 are provided along the &lt;100&gt; direction. In this case, the crystal sub-grain boundaries 150 are defined along the &lt;100&gt; direction, similarly to the stripes of the antireflection films 104.
It has been recognized that piezoresistance effects of piezo resistances, which are formed by regions including such crystal sub-grain boundaries 150 of a single crystal layer, are hardly influenced by the crystal sub-grain boundaries 150 since crystal defects contained therein are of the order of 10.sup.11 cm.sup.-2 in density. In other words, it has been recognized in practice that piezo resistances having crystal sub-grain boundaries therein exhibit piezoresistance effects which are equivalent to those of piezo resistances which are prepared from bulk single crystal silicon.
FIG. 17 is a plan view showing a conventional semiconductor pressure sensor employing piezo resistances having SOI structures, and FIG. 18 is a sectional view of the semiconductor pressure sensor taken along the line X--X in FIG. 17. FIG. 19 is a partially enlarged view showing a part A of the semiconductor pressure sensor appearing in FIG. 17. Referring to FIGS. 17 to 19, the conventional semiconductor pressure sensor comprises a single crystal silicon substrate 201, a diaphragm 208 which is formed in a prescribed region of a rear surface of the single crystal silicon substrate 201, a silicon oxide film 202 which is formed on a prescribed region of a major surface of the single crystal silicon substrate 201, dot seeds 203 which are formed on regions, provided with no silicon oxide film 202, of the major surface of the single crystal silicon substrate 201 at prescribed intervals for serving as seed crystals, piezo resistances 204 of single crystal silicon having piezo characteristics which are formed on prescribed regions of the silicon oxide film 202, an interlayer insulating film 205 of a CVD silicon oxide film which is formed to cover the single crystal silicon substrate 201 and the piezo resistances 204 with contact holes 206 provided in prescribed regions located on the piezo resistances 204, interconnection layers 207 which are electrically connected to the piezo resistances 204 through the contact holes 206 to extend along the interlayer insulating film 205, and a protective film 209 of a plasma nitride film or a silicon oxide film which is formed to cover the interconnection layers 207 and the interlayer insulating film 205. The piezo resistances 204 having conventional SOI structures, which are formed by lateral seeding, have crystal sub-grain boundaries 250 therein. However, it has been confirmed in practice that the piezo resistances 204 having such crystal sub-grain boundaries 250 therein exhibit piezoresistance effects which are equivalent to those of piezo resistances prepared from bulk single crystal silicon, as hereinabove described.
In employment of the conventional semiconductor pressure sensor shown in FIGS. 17 to 19, it is necessary to perform output compensation with respect to its operating temperature. Namely, output compensation which is responsive to the operating temperature is required due to temperature dependence of piezoresistance effects. Excitation voltage compensation utilizing resistance temperature characteristics of the piezo resistances 204 is known as a method of such output compensation. Such excitation voltage compensation enables output compensation of high accuracy since the piezo resistances 204 also serve as temperature sensors. Therefore, the excitation voltage compensation is regarded as the best method of compensating temperature dependence of piezoresistance effects.
In the aforementioned output compensation utilizing the resistance temperature characteristics of the piezo resistances 204, it is necessary to make resistance temperature coefficients of the piezo resistances 204 higher than temperature coefficients of the piezoresistance effects. In a conventional piezo resistance which was prepared from bulk single crystal silicon, the temperature coefficient of its piezoresistance effect was about 2000 ppm/.degree.C. when impurity concentration of the piezo resistance was about 3.times.10.sup.18 cm.sup.-3. The piezo resistance exhibited a resistance temperature coefficient of about 4000 ppm/.degree.C. under the same condition. On the other hand, it has been proved that each of the piezo resistances 204 having SOI structures shown in FIGS. 17 to 19 had a considerably small resistance temperature coefficient of 1000 ppm/.degree.C. while the temperature coefficient of its piezoresistance effect was equivalent (about 2000 ppm/.degree.C.) to that of the aforementioned piezo resistance of bulk single crystal silicon. It has also been proved that the piezo resistance 204 of an SOI structure exhibited such a small resistance temperature coefficient due to crystal defects contained in the crystal sub-grain boundaries 250. Such crystal defects capture conduction carriers (electrons or holes) which are supplied by addition of an impurity, to form potential barriers. Due to such potential barriers, electric conduction of the piezo resistance 204 depends on a thermal emission current. Thus, changes of the resistance value of the piezo resistance 204 with respect to temperatures are decided by values of the potential barriers. Thus, the changes of the resistance value of the piezo resistance 204 with respect to temperatures are smaller than those of the piezo resistance prepared from bulk silicon. The resistance temperature coefficient of the piezo resistance 204 having the crystal sub-grain boundaries 250 therein inconceivably rendered smaller than that of the piezo resistance prepared from bulk single crystal silicon as the result. In the conventional piezo resistance 204 having an SOI structure, therefore, it is difficult to carry out temperature compensation in high accuracy by the excitation voltage compensation since the resistance temperature coefficient of the piezo resistance 204 is smaller than the temperature coefficient of its piezoresistance effect.
It is known that a piezoresistance effect of a piezo resistance which is prepared from silicon single crystal depends on its impurity concentration. In other words, it is known that the piezoresistance effect is increased as the impurity concentration is reduced when the piezo resistance has impurity concentration of at least 10.sup.17 cm.sup.-3. When each of the piezo resistances 204 shown in FIGS. 17 to 19 is prepared from single crystal silicon which is formed by laser recrystallization, its piezoresistance effect is increased as impurity concentration thereof is reduced. However, such reduction in impurity concentration of the piezo resistance 204 leads to increase in dispersion of the resistances value in the wafer plane. Such dispersion of the resistance value results from heterogeneity of crystal defects, contained in the crystal sub-grain boundaries 250, which are of the order of 10.sup.11 cm.sup.-2 in density. Namely, the crystal defects contained in the crystal sub-grain boundaries 250 capture conduction carriers(electrons or holes) which are supplied by addition of an impurity, to form potential barriers. Such potential barriers are increased as the piezo resistance 204 is reduced in impurity concentration. Such increased potential barriers are largely dispersed due to dispersion of the crystal defects in density. It is conceivable that the dispersion of the resistance value of the piezo resistance is consequently increased as the impurity concentration is reduced. In the conventional piezo resistance of an SOI structure, therefore, it is difficult to increase the piezoresistance effect while suppressing dispersion of the resistance value.